1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory comprising a resistant element such as a silicide blown electric fuse which can be manufactured through a standard CMOS process.
2. Description of the Related Art
In a semiconductor memory with analog trimming or memory redundancy, fuse elements are widely used for achieving the functions. Fabrication of the fuses has become increasingly difficult due to its micronized process so that there has been a demand for developing a substitute technique. For meeting such demand, there is proposed an electric fuse which can be easily manufactured by a standard CMOS process to be used for storing data by using a difference of the resistance before and after blowing silicide.
The related art is disclosed, for example, in U.S. Pat. No. 6,384,664 “DIFFERENTIAL VOLTAGE SENSE CIRCUIT TO DETECT THE STATE OF A CMOS PROCESS COMPATIBLE FUSES AT LOW POWER SUPPLY VOLTAGES” (referred to as a first related art) and “A PROM Element BaseDON Silicide Agglomeratin of Poly Fuses in a MOS Logic Process” IEEE 1997, Mohsen AlaVi et al., (referred to as a second related art).
FIG. 10 shows an exemplifier illustration of the first related art. In FIG. 10, reference numeral 101 is an electric fuse. 102 is a reference resistance as a comparative target of the resistance value of the electric fuse 101. 105, 106, 112, and 113 are PMOS transistors. 107, 108, 109, 110, and 111 are NMOS transistors. 114 and 115 are inverter circuits. 116 is a NOR circuit comprising two inputs.
Between a power source VDDH and GND, the electric fuse 101, the NMOS transistor 103, the reference resistance 102, and the NMOS transistor 104 are disposed, respectively. The PMOS transistors 105, 106 and the NMOS transistors 107, 108 constitute a cross couple. Drains of the NMOS transistors 109, 110 are coupled to sources of the NMOS transistors 107, 108, respectively. The NMOS transistor 111 is disposed between the sources of the NMOS transistor 109, 110 and the GND. The PMOS transistors 112, 113 are disposed between the power source VDDH and cross couple nodes N3, N4. The outputs /DO, DO of the inverter circuits 114, 115 are inputted to the NOR circuit 116. An output signal READ of the NOR circuit 116 is inputted to the NMOS transistors 103, 104.
The operation of the semiconductor memory used in a conventional read-out circuit formed as described above will be described by referring to a timing chart of FIG. 11.
In a standby state where a reading-out action is not performed, /READ is “0” and the NMOS transistor 111 to which the /READ is inputted is in OFF state. The cross couple nodes N3, N4 are pre-charged to VDDH by the PMOS transistors 112, 113. The outputs /DO, DO of the inverter circuits 114, 115 are both “0”. Thereby, the output READ of the NOR circuit 116 becomes “1” so that the NMOS transistors 103, 104 are in ON state.
At this time, due to a flow of electric current via the NMOS transistor 103, 104, there is a voltage drop caused in the electric fuse 101 and the reference resistance 102. With this, a voltage N1 at the end part of the electric fuse 101 and a voltage N2 at the end part of the reference resistance 102 come to have an analog voltage value which is lower than the VDDH for the amount of the voltage drop. The voltages N1, N2 are inputted to the gates of the NMOS transistors 109, 110, respectively.
At this time, the reading-out action is started. When the /READ changes from “0” to “1”, the PMOS transistors 112, 113 become OFF and the NMOS transistor 111 becomes ON. In that state, both the NMOS transistors 109, 110 are in ON state since the voltages N1, N2 inputted to the gates thereof is lower than the VDDH. Therefore, both cross couple nodes N3, N4 start to discharge from the pre-charge level VDDH to the GND.
The rate of discharge at this time depends on the voltages N1, N2 inputted to the gates of the NMOS transistors 109, 110 and the size of device. For example, in the case where the electric fuse 101 is not blown (having the initial resistance value), the voltage drop by the electric fuse 101 is smaller than he voltage drop by the reference resistance 102. Thus, it becomes (N1>N2). Therefore, the capacity of having the flow of the electric current becomes higher in the NMOS transistor 110 which has the voltage N1 inputted to its gate than in the NMOS transistor 109 which has the voltage N2 inputted to its gate. Accordingly, the cross couple node N3 is discharged faster than the cross couple node N4. As a result, there is a small voltage difference generated between both cross couple nodes N3, N4. The small voltage difference is amplified and, at last, the CMOS voltage level of the cross couple node N3 becomes “0” and that of the cross couple node N4 becomes “1”.
Now, let's look into the outputs of the inverter circuits 114 and 115. In the standby state, the cross couple nodes N3, N4 are pre-charged to the VDDH and become “0”. However, when the voltage difference between the voltages N1, N2 transmitted to the cross couple nodes N3, N4 are compared and amplified, the cross couple node N3 becomes “0” and the cross couple node N4 becomes “1”. Thus, the output /DO becomes “1” and the output DO becomes “0”. Accordingly, the output READ of the NOR circuit 116 to which these outputs /DO and DO are inputted changes from “1” to “0” and the NMOS transistors 103, 104 become OFF. Therefore, the voltages N1, N2 at the intermediate voltage level becomes VDDH via the electric fuse 101 and the reference resistance 102.
As described above, the READ is “1” from the supply of power till starting the reading out action, and the NMOS transistors 103, 104 are in ON state. The intermediate-level voltages N1, N2 are generated at the end parts of the electric fuse 101 and the reference resistance 102 in accordance with the resistance values thereof. However, when the reading out action is started and the comparing/amplifying action of the voltage difference between the voltages N1, N2 is completed, the result is fed back. Thus, the NMOS transistors 103, 104 become OFF and the voltages N1, N2 both become VDDH.
In the process of the reading out action, in the comparing/amplifying circuit, the gate voltages of the NMOS transistors 109, 110 both become VDDH. However, data is already latched by being compared and amplified so that the data is kept stored.
As described above, in the conventional structure, the voltage levels N1 and N2, which are generated in accordance with the resistance value of the electric fuse 101 and that of the reference resistance 102, are inputted to the gates of the NMOS transistors 109, 110. Thus, in the case where, for example, elements which are formed through a manufacturing process with a large dispersion in Vt (threshold voltage) are mounted as the MOS transistors 109, 110, or external noise is applied at the time of reading out action, the following inconveniences are generated. That is, during the process of comparing and amplifying the small difference between the voltages, which is caused when the cross couple nodes N3, N4 are discharged from VDDH, there may cause mis-latching of data thus generating reading out failure.
Further, from the supply of the power until starting the reading out action, the READ is “1”, the NMOS transistors 103, 104 are constantly ON, and the electric current is kept flown in the electric fuse 101 and the reference resistance 102. Therefore, in such a system LSI which uses a plurality of semiconductor memories with a memory redundant function, consumption of electric current is increased.
Further, in the comparing/amplifying circuit, the data, when determined once by the reading out action, is constantly held in the cross couple circuit (the PMOS transistors 105, 106 and the NMOS transistors 107, 108) by keeping the NMOS transistor 111 ON. Therefore, “0” is always applied to the gate of either the PMOS transistor 105 or 106 so that there may be a risk of deteriorating the PMOS transistor.